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publication number S71WS-N_00 revision a amendment 6 issue date july 19, 2006 S71WS-N S71WS-N cover sheet stacked multi-chip product (mcp) 1.8 volt-only simu ltaneous read/write, burst-mode flash memory with cellularram ? data sheet (advance information) notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product describ ed herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
ii S71WS-N S71WS-N_00_a6 july 19, 2006 data sheet (advance information) notice on data sheet designations spansion inc. issues data sheets with advance informati on or preliminary designations to advise readers of product information or int ended specifications throu ghout the product life cycle, including development, qualification, initial production, and fu ll production. in all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. the following descriptions of spansion data sheet designations are presented here to highlight their presence and definitions. advance information the advance information designation indicates that spansion inc. is developing one or more specific products, but has not committed any design to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore places the following c onditions upon advance information content: ?this document contains information on one or mo re products under development at spansion inc. the information is intended to help you evaluate th is product. do not design in this product without contacting the factory. spansion inc. reserves t he right to change or discont inue work on this proposed product without notice.? preliminary the preliminary designation indicates that the produc t development has progressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial produc tion, and the subsequent phases in t he manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these as pects of production under consideration. spansion places the following conditions upon preliminary content: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this doc ument may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designations (advance information, preliminary, or full production). this type of docum ent distinguishes these prod ucts and their designations wherever necessary, typically on the first page, t he ordering information page, and pages with the dc characteristics table and the ac erase and program ta ble (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of time such that no changes or only nominal changes are expected, the preliminary designation is remove d from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as t he addition or deletion of a speed option, temperature range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographical error or incorre ct specification. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical sp ecifications regarding the spansion product(s) described herein. spansi on inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or mo difications to the valid comb inations offered may occur.? questions regarding these docum ent designations may be directed to your local sales office.
this document contains information on one or more products under development at spansion inc. the information is intended to he lp you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed pr oduct without notice. publication number S71WS-N_00 revision a amendment 6 issue date july 19, 2006 features ? power supply voltage of 1.7 v to 1.95 v ? burst speed: 54 mhz, 66 mhz, 80 mhz ? package ? 8 x 11.6 mm, 9 x 12 mm ? operating temperature ? wireless, ?25 c to +85 c general description the S71WS-N series is a product line of stacked multi-chip product (mcp) packages and consists of the following items: ? one or more flash memory die (for the s71ws512n, two s29ws256n devices are used) ? cellularram type 2 psram the products covered by this document are listed in the table below. for details about their s pecifications, please refer to th e individual constituent datasheet for further details. for detailed specifications, please refer to the individual data sheets. S71WS-N stacked multi-chip product (mcp) 1.8 volt-only simu ltaneous read/write, burst-mode flash memory with cellularram ? data sheet (advance information) flash density psram 32 mb 64 mb 128 mb s29ws128n s71ws128nb0 s71ws128nc0 s29ws256n s71ws256nc0 s71ws256nd0 s29ws512n s71ws512nc0 s71ws512nd0 document publication identification number (pid) s29ws-n s29ws-n_00 128 m cellularram type 2 cellram_04 32 m cellularram type 2 cellram_06 64 m cellularram type 2 cellram_07
2 S71WS-N S71WS-N_00_a6 july 19, 2006 data sheet (advance information) 1. product selector guide note: 0 (protected), 1 (unprotected [default state]) device model numbers flash psram density (mb) flash speed (mhz) psram speed (mhz) dyb power-up state ( see note ) psram (cellular ram) supplier package (mm) s71ws128nb0 ak ws128n 32 54 54 0 2 8.0x11.6x1.2 ap 1 aj 66 66 0 an 1 ah 80 80 0 am 1 s71ws128nc0 ak ws128n 64 54 54 0 2 8.0x11.6x1.2 ap 1 aj 66 66 0 an 1 ah 80 80 0 am 1 s71ws256nc0 ak ws256n 64 54 54 0 2 11.6x8.0x1.2 ap 1 aj 66 66 0 2 an 1 ah 80 80 0 2 am 1 s71ws256nd0 yk 128 54 54 0 2 9x12x1.2 yp 1 yj 66 66 0 yn 1 yh 80 80 0 ym 1 s71ws512nc0 ak ws512n 64 54 54 0 2 11.6x8.0x1.2 ap 1 tj 66 66 0 2 11.6x8.0x1.4 tn 1 th 80 80 0 2 tm 1 s71ws512nd0 ek 128 54 54 0 2 9x12x1.4 ep 1 ej 66 66 0 en 1 eh 80 80 0 em 1
july 19, 2006 S71WS-N_00_a6 S71WS-N 3 data sheet (advance information) 2. ordering information the order number is formed by a valid combinations of the following: 2.1 valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. package marking note: the package marking omits the leading s from the ordering part number. s71ws 256 n c 0 ba w a k 0 packing type 0=tray 2 = 7? tape and reel 3 = 13? tape and reel ram supplier, dyb power up, speed combinations k = 2 = cellularram 2, 0, 54 mhz p = 2 = cellularram 2, 1, 54 mhz j = 2 = cellularram 2, 0, 66 mhz n = 2 = cellularram 2, 1, 66 mhz h = 2 = cellularram 2, 0, 80 mhz m = 2 = cellularram 2, 1, 80 mhz package modifier a = 8x11.6x1.2 mm, 84-ball fbga t = 8x11.6x1.4 mm, 84-ball fbga e = 9x12x1.4 mm, 84-ball fbga y = 9x12x1.2 mm, 84-ball fbga temperature range w = wireless (-25c to +85c) package type ba = very thin fine-pitch bga, lead (pb)-free compliant package bf = very thin fine-pitch bga, lead (pb)-free package chip contents?2 no content psram density b=32mb c=64mb d=128mb process technology n = 110-nm mirrorbit? technology code flash density 512= 512 mb (2x256mb) 256= 256 mb 128= 128 mb product family s71ws = multi-chip product, 1.8 volt-only simultaneous read/write burst mode flash memory + psram table 2.1 mcp configurations and valid combinations valid combinations s71ws128n b 0baw, bfw a k, p, j, n, h, m c a k, p, j, n, h, m s71ws256n c a k, p, j, n, h, m d y k, p, j, n, h, m s71ws512n c a k, p, h, m t j, n, h, m d e k, p, j, n, h, m
4 S71WS-N S71WS-N_00_a6 july 19, 2006 data sheet (advance information) 3. input/output descriptions ta b l e 3 . 1 identifies the input and output package connections provided on the device. table 3.1 input/output descriptions symbol description a23-a0 address inputs dq15-dq0 data input/output oe# output enable input. asynchronous relative to clk for the burst mode. we# write enable input. v ss ground nc no connect; not connected internally rdy ready output. indicates the status of the burst read. the wait# pin of the psram is tied to rdy. clk clock input. in burst mode, after the initial word is output, subsequent active edges of clk increment the internal address counter. should be at v il or v ih while in asynchronous mode avd# address valid input. indicates to device that the valid address is present on the address inputs. low = for asynchronous mode, indicates valid address; fo r burst mode, causes starti ng address to be latched. high = device ignores address inputs f-rst# hardware reset input. low = device resets and returns to reading array data f-wp# hardware write protect input. at v il , disables program and erase functions in the four outermost sectors. should be at v ih for all other conditions. f-acc accelerated input. at v hh , accelerates programming; automatically places device in unlock bypass mode. at v il , disables all program and erase functions. should be at v ih for all other conditions. r-ce1# chip-enable input for psram. f1-ce# chip-enable input for flash 1. asynchronous relative to clk for burst mode. f2-ce# chip-enable input for flash 2. asynchronous relative to clk for burst mode. this applies to the 512mb mcp only. r-cre control register enable (psram). for cellularram only. f-vcc flash 1.8 volt-only single power supply. r-vcc psram power supply. r-ub# upper byte control (psram). r-lb# lower byte control (psram) dnu do not use
july 19, 2006 S71WS-N_00_a6 S71WS-N 5 data sheet (advance information) 4. mcp block diagram notes: 1. r-cre is only present in cellularram-compatible psram. 2. for 1 flash + psram, f1-ce# = ce#. for 2 flash + psram, ce# = f1-ce# and f2-ce# is the chip-enable pin for the second flash. 3. only needed for s71ws512n. 4. for the 128m psram devices, there are 23 shared addresses. 5. connection diagrams/physical dimensions this section contains the i/o designations and package specifications for the S71WS-N. 5.1 special handling instructions for fbga packages special handling is required for flash memory products in fbga packages. flash memory devices in fbga packages may be damaged if exposed to ultrasonic cleaning methods. the package and/or data integrity may be compromised if t he package body is exposed to temperatures above 150c for prolonged periods of time. v id v cc rdy psram flash 1 dq15 to dq0 flash-only address shared address f1-ce# acc r-ub# r-ce2 r-cre r-vcc v cc v ccq f-vcc 22 clk clk wp# oe# we# f-rst# avd# ce# acc wp# oe# we# reset# avd# rdy v ss v ssq dq15 to dq0 16 i/o15 to i/o0 16 r-ce1# ce# we# oe# ub# r-lb# lb# 22 f2-ce# clk avd# flash 2 wait# cre# ( note 1 ) ( note 2 ) ( note 2 ) ( note 4 )
6 S71WS-N S71WS-N_00_a6 july 19, 2006 data sheet (advance information) 5.2 connection diagrams 5.2.1 cellularram based pinout notes: 1. in mcps based on a single s29ws256n (s71ws256n), ball b5 is rfu. in mcp's based on two s29ws256n (s71ws512), ball b5 is f2-ce#. 2. addresses are shared between flash and ram depending on the density of the psram. mcp flash-only addresses shared addresses s71ws128nb0 a22-a21 a20-a0 s71ws128nc0 a22 a21-a0 s71ws256nc0 a23 ? a22 a21 ? a0 s71ws256nd0 a23 a22 ? a0 s71ws512nc0 a23 ? a22 a21-a0 s71ws512nd0 a23 a22-a0 a7 a3 a2 dq8 dq14 r-ce1# r-lb# acc we# a8 a11 c3 c4 c5 c6 c7 c8 a6 r-ub# f-rst# rfu a19 a12 a15 d2 d3 d4 d5 d6 d7 d8 d9 a5 a18 rdy a20 a9 a13 a21 e2 e3 e4 e5 e6 e7 e8 e9 a1 a4 a17 a10 a14 a22 f2 f3 f4 f7 f8 f9 v ss dq1 a0 dq6 rfu a16 g3 g4 g2 g7 g8 g9 f1-ce# dq0 oe# dq9 dq3 dq4 dq13 dq15 r-cre h2 h3 h4 h5 h6 h7 h8 h9 dq10 f-vcc r-vcc dq12 dq7 v ss j2 j3 j4 j5 j6 j7 j8 j9 dq2 dq11 rfu dq5 k3 k8 k4 k5 k6 k7 rfu a23 f5 rfu rfu g5 f6 g6 rfu clk f2-ce# rfu rfu rfu b3 b4 b5 b6 b7 b8 rfu rfu f-vcc rfu rfu rfu l3 l4 l5 l6 l7 l8 b2 b9 c9 c2 k2 k9 l9 l2 avd# rfu rfu rfu rfu f-wp# rfu rfu a1 a10 m1 m10 dnu dnu dnu dnu 1st flash only shared flash shared only legend ram only 2nd flash only 84-ball fine-pitch ball grid array cellularram-based pinout (top view, balls facing down)
july 19, 2006 S71WS-N_00_a6 S71WS-N 7 data sheet (advance information) 5.2.2 look-ahead pinout for future designs please refer to the design-in scalable wireless solutions with spansion products application note (publication number: design_scalable_wir eless_a0_e). contact your local spansion sales representative for more details. 5.3 physical dimensions 5.3.1 tla084?84-ball fine-pitch ball gr id array (fbga) 11.6 x 8.0 x 1.2 mm 3372-2 \ 16-038.22a package tla 084 jedec n/a d x e 11.60 mm x 8.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10, e1,e10,f1,f10,g1,g10, h1,h10,j1,j10,k1,k10,l1,l10, m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 c a b m c m 0.08 pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view
8 S71WS-N S71WS-N_00_a6 july 19, 2006 data sheet (advance information) 5.3.2 fta084?84-ball fine-pitch ball gr id array (fbga) 11.6 x 8.0 x 1.4 mm 3388 \ 16-038.21a package fta 084 jedec n/a d x e 11.60 mm x 8.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.17 --- --- ball height a2 1.02 --- 1.17 body thickness d 11.60 bsc. body size e 8.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10,e1,e10 f1,f10,g1,g10,h1,h10 j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. (2x) c 0.08 0.20 c c 6 b side view 84x a1 a2 a 0.15 m c mc ab 0.08 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd a e b c 0.15 d c 0.15 (2x) index mark 10 top view corner pin a1
july 19, 2006 S71WS-N_00_a6 S71WS-N 9 data sheet (advance information) 5.3.3 tsd084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.2 mm 3426\ 16-038.2 2 package tsd 084 jedec n/a d x e 12.00 mm x 9.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.17 --- --- ball height a2 0.81 --- 0.94 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a 0.15 m c mc ab 0.08 pin a1 bottom view ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd
10 S71WS-N S71WS-N_00_a6 july 19, 2006 data sheet (advance information) 5.3.4 fea084?84-ball fine-pitch ball grid array (fbga) 12.0 x 9.0 x 1.4 mm note: bsc is an ansi standard for basic space centering. 3423 \ 16-038.21 a package fea 084 jedec n/a d x e 12.00 mm x 9.00 mm note package symbol min nom max a --- --- 1.40 profile a1 0.10 --- --- ball height a2 1.11 --- 1.26 body thickness d 12.00 bsc. body size e 9.00 bsc. body size d1 8.80 bsc. matrix footprint e1 7.20 bsc. matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 84 ball count ? b 0.35 0.40 0.45 ball diameter ee 0.80 bsc. ball pitch ed 0.80 bsc ball pitch sd / se 0.40 bsc. solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b1,b10,c1,c10,d1,d10 e1,e10,f1,f10,g1,g10 h1,h10,j1,j10,k1,k10,l1,l10 m2,m3,m4,m5,m6,m7,m8,m9 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populted solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. n/a 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. c 0.08 0.20 c a e b c 0.15 (2x) c d c 0.15 (2x) index mark 10 6 b top view side view corner 84x a1 a2 a pin a1 ml e1 7 se a d1 ed dc e f g h j k 10 8 9 7 6 4 3 2 1 ee 5 b pin a1 corner 7 sd bottom view 0.15 c a b m c m 0.08
july 19, 2006 S71WS-N_00_a6 S71WS-N 11 data sheet (advance information) 6. revision history colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, genera l office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers t hat, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic contro l, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intole rable (i.e., submersible repeater and artifi cial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with abo ve-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect agains t injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document r epresent goods or technologies s ubject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export ad ministration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subjec t to change without notice. this document ma y contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warran ty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2004-2006 spansion inc. all rights reserved. spansion, the spansion logo, mirrorbit, ornand, hd-sim, and combinatio ns thereof are trademarks of spansion inc. other names are for informational purposes only and may be trademarks of their respecti ve owners. section description revision a (february 1, 2004) initial release. revision a1 (february 9, 2005) global updated document to include burst speed of 66 mhz updated publication number revision a2 (march 31, 2005) global updated product selector guide and ordering information tables revision a3 (may 2, 2005) global added 80 mhz speed options to: product selector guide ordering information table valid combination table revision a4 (august 25, 2005) global replaced module cellram_00_a0 with cellram_03 and cellram_04 revision a5 (february 7, 2006) global updated product selector guide with new options updated the ordering part number table updated the valid combinations table removed the look-ahead diagram revision a6 (july 19, 2006) global reformatted document to new template added reference to 32 mb cellram module

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